1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a nonvolatile semiconductor memory device storing data in a nonvolatile manner. More particularly, the present invention relates to a configuration for a data access in a nonvolatile semiconductor memory device with a virtual ground array in which memory cells on adjacent two columns in a row direction are connected to a common bit line.
2. Description of the Background Art
In a nonvolatile semiconductor memory device storing data in a nonvolatile manner, there is known an insulating film charge trap type memory in which charges are trapped in an insulating film under a control gate to store data.
FIG. 25 is a schematic diagram showing a sectional structure of a conventional insulating film charge trap type memory cell. In FIG. 25, an insulating film charge trap type memory cell includes: buried diffusion layers 901a and 901b formed on a surface of a semiconductor substrate region 900; a multilayer insulating film 903 formed on a substrate region between buried diffusion layers 901a and 901b; and a conductive layer 904 formed on multilayer insulating film 903.
Buried diffusion layers 901a and 901b are formed extending in a column direction and used as bit lines. Conductive layer 904 is formed extending in a row direction, used as a word line to transmit a row select signal, and also used as a control gate of the memory cell.
Multilayer insulating film 903 is arranged in parallel to conductive layer 904 extending in a word line direction. Multilayer insulating film 903 has a multilayer structure constructed of an oxide film 903a, a nitride film 903b and an oxide film 903c, and charges are accumulated in a region of nitride film 903b between oxide films 903a and 903c. 
In the following description, the term “data programming” is used to indicate an operation of accumulating charges (electrons) in insulating film 903b. In this state, it is assumed that data at H level is written. In storage of L level data, no electron is accumulated. In the insulating charge trap type memory cell, there exist two regions for accumulating charges: a right bit region BT1 and a left bit region BT2.
When programming is performed to right bit region BT1, a voltage of 9 V is applied to control gate (a gate electrode layer) 904 and a voltage of 4.5 to 6 V is applied to diffusion bit line region (an impurity region; buried diffusion region) 901b. Diffusion bit line region (an impurity region; buried diffusion region) 901a is set to a ground voltage level. In this state, a channel is formed on the surface of substrate region 900 in accordance with the voltage applied to gate electrode 904 and a current I flows from diffusion bit line region 901b to diffusion bit line region 901a, as shown with an arrow mark in a left direction in FIG. 25.
Current I flowing in the channel region is accelerated in a vertical direction under an influence of the voltage applied to gate electrode layer 904, and electrons (channel hot electrons) are stored into nitride film 903b and thus accumulated in right bit region BT1. Since a mobility of an electron is small in nitride region 903b, right bit region BT1 is formed only in a region in the vicinity of the drain region in self-alignment with the drain region (since channel hot electrons are generated in a drain high electric field and then accelerated to be accumulated in nitride film 903b).
On the other hand, when electrons are accumulated in left bit region BT2, a voltage of 4.5 to 6 V is applied to diffusion bit line region 901a, and diffusion bit line region 901b is set to ground voltage level. A voltage of 9 V is applied to gate electrode layer 904. In this case, current I flows, as shown with an arrow mark in a right direction in FIG. 25, from diffusion bit line region 901a to diffusion bit line region 901b, and channel hot electrons generated by the drain high electric field is accelerated by the voltage applied to gate electrode 904 to be stored into nitride film 903b. Thereby, electrons are accumulated in left bit region BT2.
In other words, in a programming operation, channel hot electrons (CHE) are generated and trapped in nitride film 903b. A state where electrons are injected in the charge accumulating region is referred to as a programmed state (write state). In the programmed state, electrons are injected into an effective charge accumulating region, which results in a high threshold voltage of a memory cell transistor in this region.
In data reading, current I is caused to flow, as shown with an arrow mark in FIG. 25, in a direction opposite to that in a programming operation. Specifically, when storage data in right bit region BT1 is read out, a voltage of, for example, 1.5 to 2 V is applied to diffusion bit line region 901a and diffusion bit line region 901b is set to ground voltage level. A read voltage of, for example, 4 V is applied to gate electrode layer 904. In this case, a punch-through generates due to widening of a depletion layer in left bit region BT2, and a threshold voltage in a region in the vicinity of left bit region BT2 exerts no influence on a read current. When a current flows from diffusion bit line region 901a to diffusion bit line region 901b in data read operation, a current amount flowing through the channel region is determined according to an electron amount accumulated in right bit region BT1. By detecting the current amount, data stored in right bit region BT1 can be read.
On the other hand, when data stored in right bit region BT2 is read, a voltage of 1.5 to 2 V is applied to diffusion bit line region 901b and diffusion bit line region 901a is set to ground voltage level. A voltage of the order of 4 V is applied to gate electrode layer 904. A punch-through generates in the substrate surface region in the vicinity of right bit region BT1, a depletion layer is merely widened in the right bit region and a current corresponding to an electron amount accumulated in left bit region BT2 flows between diffusion bit lines 901b and 901a. By detecting the current amount, data stored in left region BT2 is read.
Usually, a direction along which a current flows in a memory cell in programming is referred to as a forward direction, and a direction along which a current flows in data reading is referred to as a reverse direction. Therefore, as shown with arrow marks in FIG. 25, a forward direction and a reverse direction in operations for right bit region BT1 are reversed in those for left bit region BT2.
Various erasing methods of storage data have been proposed. One is a method in which a current is caused to flow in a reverse direction to generate channel hot holes to inject the channel hot holes into the nitride film for causing recombination of accumulated electrons with hot holes to neutralize the accumulated electrons. The second is a method in which a voltage is applied between nitride film 903b and gate electrode layer 904 to extract electrons accumulated in nitride film 903b through gate electrode 904. Since gate electrode layer 904 forms a word line as described later and is driven by a row select circuit not shown, electrons is eventually extracted by the row select circuit in the second method.
The third is a method in which a current is caused to flow by a (inter-band) tunneling current between nitride film 903b and the drain region (a diffusion bit line) to extract electrons from nitride film 903b. As to an erasure operation, any of erase operations may be employed. In an erasure operation as well, erasure is individually performed on each of right bit region BT1 and left bit line region BT2.
FIG. 26 is a diagram showing an electrically equivalent circuit of a memory cell and applied voltages in a programming operation. In FIG. 26, there are representatively shown memory cells arranged in two rows and three columns. In FIG. 26, there are shown memory cells MC each formed of a floating gate type transistor. In this insulating film charge trap type memory cell, the floating gate of a floating gate type transistor is formed using not polysilicon, but nitride film (903b).
Word lines WLa and WLb are provided in correspondence to the respective memory cell rows and the gate electrode layers (control gates) of memory cells on a corresponding row are connected to a corresponding word line. Bit lines BLa to BLc are provided in correspondence to memory cell columns. Bit lines BLa to BLc are each shared by memory cells MC adjacent to each other in a row direction.
Now, it is considered a programming operation on right bit region BT1 of memory cell MC1 arranged in correspondence to crossings between word line WLb and bit lines BLb and BLc. Writing (programming) of data is performed by causing a current to flow in a forward direction. Therefore, in this case, a voltage of 4.5 to 6 V is applied onto bit line BLc and bit line BLb is held at ground voltage level. Bit line BLa is maintained in a floating state. Word lines WLa and W1b are set to 0 V and 9 V, respectively. In this state, in memory cell MC, a current flows from bit line BLc to bit line BLb to generate channel hot electrons, e and generated electrons are stored in right bit region BT1.
In a memory cell MC3 adjacent to memory cell MC1 in a row direction, since bit line BLa is in a floating state and no channel current flows, no channel hot electron is generated, and programming is not performed.
In memory cell MC3 adjacent to memory cell MC1 in a column direction, since word line WLa is maintained at ground voltage level to hold the memory cell transistor in a non-conductive state, no channel current flows, and programming is not performed.
Therefore, even in a configuration in which a bit line is shared by memory cells adjacent to each other in a row direction, programming can be correctly performed only in a memory cell of a programming object.
FIG. 27 is a diagram showing applied voltages in data reading. In FIG. 27, when data stored in right bit region BT1 of memory cell MC1 is read out, a voltage of 1.5 to 2 V is applied onto bit line BLb, and bit line BLc is maintained at ground voltage level. Word lines WLa and WLb are set to 0 V and 4 V, respectively. In this state, current I corresponding to an amount of electrons accumulated in right bit region BT1 of memory cell MC1 flows from bit line BLb to bit line BLc. A magnitude of current I is detected to read data stored in right bit region BT1. In a read operation, bit line BLa is in a floating state and even if read voltage of 1.5 to 2 V is applied onto bit line BLb in memory cell MC2, no current flows in memory cell MC2. Therefore, current I of a magnitude corresponding to data stored in right bit region BT1 of memory cell MC1 can be caused to flow correctly.
When data in left bit region BT2 of memory cell MC1 is read, a voltage of 1.5 to 2 V is applied onto bit line BLc and ground voltage is applied to bit line BLb. In this case, a bit line on the right side of bit line BLc is maintained in a floating state.
FIG. 28 is a schematic diagram showing a configuration of a data read section of a conventional nonvolatile semiconductor device. In FIG. 28, the data read section includes: a constant current source 920 coupled to a bit line BL corresponding to a selected column through a column select gate 915, and supplying a read voltage together with a constant current IR to selected bit line BL; a capacitive element 921 charged by a shunt current Is from constant current source 920; and an amplifying circuit 922 generating internal read data RT in accordance with a charged voltage of capacitive element 921. Amplifying circuit 922 is formed of, for example, a differentially amplifying circuit and compares the charged voltage of capacitive element 921 with a prescribed reference voltage to generate binary read data RD.
Bit line BL is connected to a virtual source line VSL through memory cell MC. Virtual source line VSL is formed of a bit line BL on an adjacent column and in data reading, virtual source line VSL is maintained at ground voltage level. A column select signal on column select line CSL is applied to column select gate 915.
In the configuration of the internal data read section shown in FIG. 28, a value of the shunt current Is supplied to capacitive element 912 is different according to a magnitude of current Ib flowing into virtual source line VSL from bit line BL, and therefore, changes according to storage data in memory cell MC. Therefore, a charged voltage of capacitive element 921 in a prescribed period is different according to storage data in memory cell MC. By detecting and amplifying the charged voltage of capacitive element 921 with amplifying circuit 922, internal read data RD is generated.
Capacitive element 921 is once discharged to ground voltage level through a discharging switch not shown prior to data reading.
In a configuration in which a bit line is shared by adjacent memory cells as described above, a bit line is used as a virtual source line according to a selected memory in a program mode and a data read mode, and maintained at ground voltage level. Such an array configuration is referred to as a “virtual GND (ground) array” configuration.
In such a virtual GND array configuration, since a bit line is shared by two memory cells adjacent to each other in a row direction, a bit line in a floating state and a bit line in a ground voltage state are arranged on opposite sides with respect to a bit line receiving a program high voltage in programming. Therefore, a possibility arises that a current flowing in a bit line connecting to a memory cell of a programming object flows into a bit line in a floating state through an adjacent memory cell. In such a case, an amount of electrons injected into the insulating film (nitride film) of the memory cell of interest becomes insufficient, thereby impeding correct programming of data.
While it can be considered that a programming period is extended for reliable programming, current flows in a bit line in a floating state in this case, which would increase current consumption.
In data reading as well, likewise, a bit line at a ground voltage level and a bit line in a floating state are arranged on opposite sides with respect to a bit line receiving a read voltage. Therefore, in this state as well, a possibility arises that a current flows from a bit line connecting to a memory cell of a reading object to a bit line in a floating state. If storage data in the memory cell of interest is data corresponding to a programmed (write) state, a possibility arises that a erroneous determination is made that the memory cell is in an erased state, to impede a correct data reading.
Since a bit line of a programming/reading object is shared by memory cells adjacent to each other in a row direction, bit lines at a ground voltage level and in a floating state, respectively, are arranged oppositely with respect to the bit line of a programming/reading object. Therefore, in one memory block, programming/data reading can be performed only on one memory cell, thereby impeding high-speed data writing/reading. There arises a problem that a processing system efficiently performing a processing is difficult because of a small read data bit width and accordingly a small data band width.
In programming, an external access is prohibited and a voltage necessary for writing of data is generated internally to perform writing. Charges need to be injected into an insulating film in programming and a cycle time for data writing is longer than a cycle time for data reading. Therefore, a cycle time for data writing determines an access time of the semiconductor memory device, which impedes a high speed access.